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“Capture the Bug”, an international design validation hackathon that will detect design errors and understand that debugging is in progress
“Capture the Bug”, an international design verification hackathon to uncover design flaws and understand debugging, is being conducted by the National Institute of Electronics and Information Technology (NIELIT) with over 2,000 candidates participating.
The Chips to Start-up (C2S) event is associated with the state branch of the Institute of Electronic and Electrical Engineers – Robotics and Automation Society (IEEE RAS) and the Indian Institute of Technology (IIT) Madras. Union Government for training engineers in Very Large Scale Integration (VLSI) and Embedded Systems Design.
Event coordinators say the C2S program focuses on fostering innovation, building domestic capacity to ensure hardware sovereignty and facilitating a semiconductor ecosystem with highly trained engineers. “Our hackathon on VLSI design verification is also supported by the Ministry of Electronics and Information Technology,” they added.
“Chips to Start-up has mandated NIELIT-Calicut to upskill one million candidates in this field over the next four years,” said a NIELIT official. He also explained that the three-week long hackathon conducted by NIELIT-Calicut Executive Director M.P. Pillai and researchers Jayaraj U. Kidavu and R. Nandakumar would prepare engineers in VLSI design verification practices by offering training on innovative python-based frameworks.
Inaugurated by V. Kamakoti, Director, IIT Madras, on July 15, the event is free and open to all VLSI verification enthusiasts, students and working professionals in India and abroad, according to officials at the registration desk. The only requirement is to have some basic knowledge of digital design, they said.